The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
One IC process typically performed during semiconductor device fabrication is an anneal. For example, an anneal may be used to drive-in dopants to provide a suitable dopant profile. One challenge with the increasing complexity of semiconductor devices is the presence of a loading effect, also referred to as a pattern loading effect (PLE) during an anneal process. The pattern loading effect phenomenon derives from differences in radiant energy absorption in different areas of a semiconductor device or die on account of the different patterning (e.g., pattern density, aspect ratio of features, composition/reflectivity of features, etc.). In conventional processing the effects on semiconductor device performance from the PLE is characterized during electrical test. This has its disadvantages in efficiency and effectiveness of the characterization.